Abstract. Reliable data transmission in radio communication systems largely depends on the efficiency of error correction algorithms. For low-power and real-time radio systems, the use of decoding methods with reduced computational complexity and optimized hardware resource utilization is of particular importance. In this context, multi-threshold decoding algorithms represent a promising alternative to conventional iterative decoding techniques. The purpose of this paper is to investigate and analyze the hardware implementation of multi-threshold decoding algorithms for radio communication channels. The object of the study is an error correction system comprising encoder and decoder units implemented on a programmable logic device. The research methodology includes hardware modeling, experimental verification, and comparative performance analysis.
The proposed multi-threshold decoding algorithm was implemented on an Altera Cyclone IV EP4CE6E22C8N FPGA platform and tested under laboratory conditions. Experimental results demonstrate that after 20 iterations, the bit error probability is reduced to the level of 10⁻⁸. A comparative analysis with LDPC and Turbo codes shows that the proposed solution requires approximately 40% fewer FPGA resources and achieves lower power consumption. The obtained results confirm that multi-threshold decoding is an efficient and resource-saving solution for modern radio communication systems. The proposed approach is well suited for low-power and real-time applications, providing a favorable balance between decoding performance and hardware complexity.

Keywords: decoding, channel coding, multi-threshold decoding, error control coding, programmable logic integrated circuits, FPGA, radio communication, telecommunications